Nonvolatile memory devices are capable of retaining data stored in their cells, without loss, even when power is removed. Flash memories are widely used as a type of non-volatile memory device suitable in portable information apparatuses such as mobile phones, personal digital assistants (PDAs), or digital cameras, for example.
FIG. 1 is a cross-sectional diagram of a conventional flash memory cell. Referring to FIG. 1, a flash memory cell 10 has a source 13 and a drain 14 formed of N+ impurities, and a channel region therebetween, in a semiconductor substrate 12. On the channel region are sequentially formed an insulation film 17 with a thickness of about 100 Å, and a floating gate 16. On the floating gate 16 are sequentially formed an oxide-nitride-oxide (ONO) insulation film 19 and a control gate 18. The source 13, the drain 14, the floating gate 16, the control gate 16, and the semiconductor substrate 12 are coupled to voltages Vs, Vg, Vd, and Vb, respectively, for programming, erasing, and reading the flash memory cell 10.
Flash memories are generally divided into NOR and NAND types in accordance with interconnection conditions between cells and bit lines. In a NOR flash memory, one bit line is connected to two or more cell transistors in parallel, and data is stored in the hot-electron mode and erased in the Fowler-Nordheim (F-N) tunneling mode. In a NAND flash memory, one bit line is connected to two or more cell transistors in series, and data is stored and erased in the F-N tunneling mode. The cell type (i.e., the NOR or NAND type) and the mechanism of storing and erasing data (i.e., the hot-electron mode or the F-N tunneling mode), determines the voltage levels of Vs, Vg, Vd, and Vb shown in FIG. 1. In general, NOR flash memories may be disadvantageous to high-density integration because of large current consumption, but advantageous to high-frequency operations. Alternatively, NAND flash memories may be advantageous to high-density integration because of smaller cell currents than the NOR flash memories.
Another important factor of the flash memory, along with operational performance, is reliability. Usually, the flash memory operates to repeat program and erase cycles, but the number of the program and erase cycles (i.e., P/E cycles) may be limited to a predetermined number. For example, it is permissible for a memory to carry out the erase operation through about ten thousands cycles before its memory blocks are regarded as being worn out. For another memory, it is possible to conduct the erase operation up to a hundred thousand or million cycles until its blocks are regarded as being worn out (i.e., “aged out”).
Once one or more blocks have been worn out, functional degradation occurs. In a flash memory system, the endurance of memory blocks is mostly determined by the number of P/E cycles that the blocks undergo. One of the typical factors to degrade the performance of a flash memory is a detrapping effect of electrons and holes accumulated in the flash memory cells. The detrapping effect of a flash memory cell and the problems thereof are discussed in 2001 IEEE Symposium on VLSI Technology, Digest of Technical Papers, pp. 115-116, entitled “A Novel Analysis Method of Threshold Voltage Shift due to Detrap in a multi-level Flash memory”.
FIG. 2 is a sectional diagram showing the detrapping effect of electrons and holes due to an increase in P/E cycles. FIGS. 3 and 4 are graphic diagrams showing variations of threshold voltages caused by the detrapping effect of electrons and holes. FIG. 3 shows distribution profiles of threshold voltages after programming single-level cells each storing 1-bit data per cell, and FIG. 4 shows distribution profiles of threshold voltages after programming multi-level cells each storing n-bit data (n is 2 or an integer larger than 2) per cell. Here, the floating gates accompanied with the detrapping effect are not restrictive to those of a general flash memory device, which are made of a conductive material. For example, the detrapping effect may occur in a charge-trap flash memory using an insulation film, such as Si3N4, Al2O3, HfAlO, or HfSiO, as a charge storage layer instead of a conductive floating gate.
Referring to FIG. 2, in the flash memory cell 10, a tunnel oxide forming the insulation film 17 maintains its high quality during initial programming. Therefore, the detrapping effect, which causes electrons or holes that have been injected or trapped in the floating gate 16, to be released is not significant. However, if the stress to the tunnel oxide increases, the detrapping effect may occur to thereby release electrons or holes from the floating gate 16 after a P/E operation. This detrapping effect may proceed so rapidly that the accuracy of the data states or the reliability of the flash memory cell may be severely degraded.
For example, as shown in FIGS. 3 and 4, if there is a significant detrapping effect, each distribution profile of threshold voltages may become wider than its desired model. With the wider distribution profile of threshold voltages for each of data state, state-to-state window margins become smaller, which narrows a margin between a voltage applied to a selected word line during a read operation and an edge of the threshold-voltage distribution. Moreover, since the window margin of the threshold-voltage distributions for the multi-level cells, as shown in FIG. 4, is narrower than that for single-level cells, the detrapping effect is more serious in a multi-level cell versus a single-level cell.